Janczyk G. – TechConnect Briefs

Economy driven SiC Power Electronics Technology Development supported by the ECSEL Joint Undertaking framework program funds

Bieniek T., Janczyk G., Sitnik A., Messina A., Łukasiewicz Research Network – Institute of Microelectronics and Photonics, PL

This paper presents the European project REACTION (first and euRopEAn siC eigTh Inches pilOt liNe) which was launched in 2018 to push throughout the new and European first 200mm (8”) SiC Pilot Line in the [...]

Smart Power and Power Discretes Hardware-software co-design for reliability improvement of BLDC power drivers for eMobility by key BCD Technologies running in Europe

Janczyk G., Bieniek T., Łukasiewicz Research Network – Institute of Microelectronics and Photonics, PL

Growing market of microcontroller driven electronic devices useful for workshop tools, household appliances, electromobility applications and functional gadgets market demand stimulates the increase of customer expectations for product functionality flexibility, reliability and price. IC fabrication [...]

The “first and euRopEAn siC eigTh Inches pilOt line” REACTION project as a Driver for key European SiC Technologies focused on Power Electronics Development

Bieniek T., Janczyk G., Sitnik A., Messina A., Instytut Technologii Elektronowej, PL

This paper presents the European project REACTION (first and euRopEAn siC eigTh Inches pilOt liNe) [1] [2] which was launched in 2018 to push throughout the new and European first 200mm (8”) SiC Pilot Line [...]

R3-PowerUP – the Driver for key European BCD Technologies Development focused on Smart Power and Power Discretes ICs

Janczyk G., Bieniek T., Institute of Electron Technology, PL

Numerous, growing number of power electronic applications operate below 1kV. The “300mm Pilot Line for Smart Power and Power Discretes” ECSEL project [1] (acronym R3-PowerUP) is focused on volume up-scaling of a set of 90nm [...]

European Activity for Smart Power Electronics and Power Discretes – The R3-PowerUP EU Project

Bieniek T., Janczyk G., Instytut Technologii Elektronowej, PL

Smart power ICs are key enabling components for various applications from mid-power automotive, to industrial power, battery management systems electric vehicles, domotics, indoor and outdoor lighting, computers and industrial peripherals. Power electronics serves over 30% [...]

The Multifunctional 3D Interposer Platform for HPC – Development, Measurements, Design Guidelines

Janczyk G., Bieniek T., Instytut Technologii Elektronowej, PL

This paper presents dedicated solutions developed in frame of the EU FP7 CarrICool project focused on the modular interposer system architecture providing scalable heat removal, local power delivery and optical signaling issues critical for high [...]

CarrICool – the Innovative 3D Interposer Platform for HPC Systems: Analysis, Simulations, Optimization, Practice for Reliability Improvement and Performance Increase

Janczyk G., Bieniek T., Bajurko P., Instytut Technologii Elektronowej, PL

This paper presents specific solutions being developed in frame of the CarrICool (abbr. “Modular Interposer System Architecture providing scalable Heat Removal, Power Delivery and Optical Signaling”) European FP7 project. The presented research and developed solutions [...]

Investigation on Accelerated Ageing Techniques for IC Interconnect Structures in Context of Multicriterial Optimization of 3D SiP Design Flow

Janczyk G., Bieniek T., Instytut Technologii Elektronowej, PL

Many complex chips and novel smart nanosensor systems are developed as 3D structures like SiP on SoC to implement all requested functionality and achieve performance. Such structures incorporate several modules, materials forming 3D setup which [...]

Nanolayer Interconnect Structures Ageing by Beam Resonance Method

Janczyk G., Bieniek T., Instytut Technologii Elektronowej, PL

This paper discusses important aspects of investigation on interconnects reliability and ageing which has to be considered in nanoscale. The research is ongoing and applies to structures like SiP, SoC where mechanical stress caused by [...]