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HomeAuthorsDavis J.

Authors: Davis J.

The Impact of Dielectric Coatings and Porosity of Nanoparticles on Energy Density

Davis J., Brown D., Henderson W., Anbalagan P., Georgia Institute of Technology, US
Using experimentally calibrated 3-D quasi-electrostatic simulations, various microstructural architectures of cold-pressed nanoparticle (NP) compacts for low-frequency energy storage applications are investigated. This work is built upon our investigations into metal-insulator composites [1] and dielectric composites [...]

Developing a Strategy for the Spatial Localisation and Autonomous Release of Silver Nanoparticles within Smart Implants

Newton L.A.A., Sharp D.G., Leslie R., Davis J., Nottingham Trent University, UK
A novel approach to the controlled release of silver nanoparticles from a solid state repository within microdevice/micro fluidic architectures is presented. The dynamics of their formation, mechanism and influence on particle formation and release characteristics [...]

Simple Method of Characterizing CMOS Channel Dopant Profiles Using CV Technique

Kapila D., Kulkarni M., Fernando C., Davis J., Vasanth K., Pollack G., Texas Instruments, Inc., US
In CMOS process and device simulations, characterization of complete dopant profiles in the channel region is essential for accurate simulations. We have developed a simple, fast and inexpensive methodology for characterizing CMOS channel dopant profiles [...]

Yield Prediction Under Non-Standard Data Distributions

Rao S., Saxena S., Apte P., Mozumder P.K., Davis J., Burch R., Vasanth K., Texas Instruments, Inc., US
The trend towards smaller feature sizes has increased the need to accurately characterize the distribution of process and device responses to predict and improve yield [1]. The usual approach to characterization assumes that the response [...]

PSDesigner: A Framework for Transistor Co-Optimization

Burch R., Saxena S., Mozumder P.K., Vasanth K., Davis J., Rao S., Texas Instruments, Inc., US
One challenge for modern CMOS technology is the manufacture of dissimilar transistors on a sin~le chip at minimum cost. For example, hioh performance transistors for critical paths and low power transistors can be combined to [...]

A Method of MOSFET Dopant Profile Prediction and its Use in Transistor Design

Kulkarni M., Vasanath K., Davis J., Saxena S., Pollack G., Texas Instruments, Inc., US
As MOS transistor size shrinks to sub-quartermicron dimensions, accurate knowledge of the dopant concentration in various regions of the transistor is becoming more and more important for device simulations. We have developed a methodology to [...]

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