Stanford University – Page 2 – TechConnect Briefs

Dynamics of Water in Nafion Fuel Cell Membranes: the Effects of

Moilanen D.E., Piletic I.R., Fayer M.D., Stanford University, US

The complex environment experienced by water molecules in the hydrophilic channels of Nafion membranes is studied by ultrafast infrared pump-probe spectroscopy. A wavelength dependent study of the vibrational lifetime of the O-D stretch of dilute [...]

Grain Size Distribution in CoCrPtO-Based Perpendicular Magnetic Recording Media

Hossein-Babaei F., Kwon U., Sinclair R., Stanford University, US

A multilayer disk structure based on a CoCrPtO magnetic layer is one of the material choices for fabrication of perpendicular magnetic recording media. In these devices, nano-sized (typically ~10 nm in diameter), magnetically hard cobalt-rich [...]

TEM Studies of Iron Oxide Nanoparticles for Cell Labeling and Magnetic Separation

Koh A.L., Sinclair R., Stanford University, US

One of the application areas for magnetic nanoparticles (MNPs) is in cell labeling and magnetic separation. This process involves tagging MNPs onto desired cells and then separating them from unwanted entities using a sensor which [...]

Modeling of FET Flicker Noise and Impact of Technology Scaling

Chen C-Y, Liu Y., Cao S., Dutton R., Sato-Iwanaga J., Inoue A., Sorada H., Stanford University, US

Ongoing scaling of device dimensions, including the introduction of new channel materials and device structures, as well as the incorporation of novel gate-stack materials, has major implications on noise performance metrics. In particular, flicker noise [...]

Carbon Nanotube Transistor Compact Model

Deng J., Wan G.C., Wong H.-S., Stanford University, US

The principal challenges for the semiconductor industry at the nanoscale are: (1) power and performance optimization, (2) device fabrication and control of variations at the nanoscale, and (3) integration of a diverse set of materials [...]

Carbon Nanotube Transistors with 60mV/decade Switching and its Capacitance Measurement

Lu Y., Dai H., Nishi Y., Stanford University, US

Recently, we have been able to approach the ultimate vertical scaling limit of carbon nanotube field effect transistors (FETs) and reliably achieve S ~ 60 mV/decade at room temperature, by non-covalent functionalization of single walled [...]

Effects of Scaling on Modeling of Analog RF MOS Devices

Liu Y., Cao S., Oh T.Y., Wu B., Tornblad O., Dutton R.W., Stanford University, US

This paper uses advanced TCAD tools—both IMF-based noise modeling and HB-based distortion modeling—to extract parameters of key importance in developing compact models. Additionally, the TCAD-based modeling provides insight into technology constraints that can potentially influence [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R.W., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]

Mobility Extraction and Compact Modeling for FETs Using High-K Gate Materials

Dutton R.W., Liu Y., Choi C-H, Chen T.W., Stanford University, US

This simulation work discusses the impact of direct gate tunneling on effective mobility extraction methods, particularly the Inversion Charge Pumping (ICP) method proposed recently for transistors with high-k gate dielectrics. The valence-band electron gate tunneling [...]

Three-Dimensional Logic Architecture by Four-terminal Electrical Switches (FES) beyond Two-dimensional CMOS Architecture

Fujita S., Abe K., Lee T.H., Stanford University, US

The technology expected after the lithography limit to keep increasing the number of transistors is thought to be either use of new transistors such as CNT by bottom-up process or three-dimensional (3D) architecture. We have [...]