Papers:
Simplified Half-Flash CMOS Analog-to-Digital Conveter
In this paper, we present a simplified method to construct a half-flash analog-to-digital converter (ADC) to achieve less die area consumption compared to the conventional half-flash ADC. Although the die area consumption is reduced but [...]
Pareto-Optimal Modeling for Efficient PLL Optimization
Simulation-based synthesis tools for analog circuits [1,2] face a problem extending their sizing/biasing methodology to larger block-level designs such as phase lock loops or converters: the time to fully evaluate (i.e., to fully simulate) each [...]
Scalability and High Frequency Extensions of the Vector Potential Equivalent Circuit (VPEC)
We present a complete modeling technique for inductive parasitics, based on the vector potential equivalent circuit (VPEC) topology. Novel algorithms for layout extraction and sparsification are introduced. Examples are discussed in terms of CPU time, [...]
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2
Published: March 7, 2004
Industry sector: Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 0-9728422-8-4