Pareto-Optimal Modeling for Efficient PLL Optimization

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Simulation-based synthesis tools for analog circuits [1,2] face a problem extending their sizing/biasing methodology to larger block-level designs such as phase lock loops or converters: the time to fully evaluate (i.e., to fully simulate) each complete circuit solution candidate is prohibitive inside a numerical optimization loop. In this paper, we show how to circumvent this problem with a careful mix of behavioral models for less-critical parts of the block, and pareto-optimal trade-off models for the critical components. In particular, we show how to adapt current circuit synthesis techniques to build the required tradeoff models. As a concrete example of the methodology, we show detailed simulation results from the synthesis of critical portions of a 500MHz digital frequency synthesizer PLL.

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Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2
Published: March 7, 2004
Pages: 195 - 198
Industry sector: Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 0-9728422-8-4