Improved Electric Field Decomposition Capacitance Model with 3-D Terminal and Fringe Components in Sub-28nm Interconnect

Zhang A., Li C., Liu J., He J., He X., He Y., Liu J., He J., He X., He Y., Ma G., Pan J., He J., He X., He Y., Hu G.
Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution, CN

Keywords: 3d interconnect, 3D terminal, capacitance model, electric field decomposition, terminal fringe, TSV process

In this paper, a parasitic capacitance model for a finite single three-dimensional (3-D) wire above an infinite plate in the nano-scale 3-D integrated circuit application is developed based on electric field decomposition (EFD). The capacitance components at wire ends, i.e., the 3-D terminal and terminal fringe capacitance, are considered by the 3-D electric field analysis. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of 3-D BEOL wire dimensions in the beyond 28nm CMOS process technology.

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Journal: TechConnect Briefs
Volume: TechConnect Briefs 2019
Published: June 17, 2019
Pages: 279 - 282
Industry sector: Sensors, MEMS, Electronics
Topics: Nanoelectronics, Sensors - Chemical, Physical & Bio
ISBN: 978-0-9988782-8-7