Nomoto A., Sato Y., Horio K.
Shibaura Institute of Technology, JP
Keywords: current slump, field plate, GaAs FET, two-dimensional analysis
In compound semiconductor FETs, slow current transients are often observed even if the drain voltage VD or the gate voltage VG is changed abruptly [1]. This is called drain lag or gate lag, and undesirable for circuit applications. Slow transients indicate that dc and RF I-V curves become quite different, resulting in lower RF power available than that expected from dc operation [2]. This is called current slump. These phenomena occur mainly due to surface states [1,2]. Experimentally, the introduction of field plate like Fig.1 is shown to reduce the lags and current slump [2]. However, few simulation studies on field-plate structures have been made. In previous works [3, 4], we made two-dimensional simulation of field-plate GaAs MESFETs including surface states, and found that surface-related lags and current slump can be reduced by introducing a field plate. In this work, we have further studied the field-plate effects and found that the surface-state-related lags and current slump could be completely removed when the passivation layer is thin and the field plate length is comparable to or longer than the surface-state-layer length.
Journal: TechConnect Briefs
Volume: 4, Advanced Manufacturing, Electronics and Microsystems: TechConnect Briefs 2016
Published: May 22, 2016
Pages: 117 - 121
Industry sector: Sensors, MEMS, Electronics
Topic: MEMS & NEMS Devices, Modeling & Applications
ISBN: 978-0-9975-1173-4