Novel Nanoelectromechanical Relay Design Procedure for Logic and Memory Applications

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NanoElectroMechanical Structures/Systems (NEMS) have been the focus of an increasing attention from researchers in recent years for the alternative they offer to conventional CMOS for application in logics, memory and in general digital circuitry. Scaled CMOS transistors indeed suffer from energy-efficiency limitations imposed by the finite sub-threshold slope (large leakage current), especially for sub 90nm devices. NEMS on the contrary exhibit low power consumption and allow new functionalities providing an ideal platform to build multifunctional nanoscale ICs. NEMS relays can indeed achieve both low effective threshold voltage and zero leakage, thus not suffering from their scaling in the same way CMOS-transistors do. This paper presents a rigorous design approach for NEMS relays taking Casimir and/or van der Waals forces into account for the static and dynamic modeling of the devices. Key in our approach is the proper definition of the critical pull-in and pull-out voltages as well as the derived non-latching and non-self-actuation conditions, thus improving on previous works that used simplified models and approximated designs.

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Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Published: June 18, 2012
Pages: 613 - 616
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Informatics, Modeling & Simulation
ISBN: 978-1-4665-6275-2