Multiple gate approach – solution of scaling and nano MOSFETS

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In the sub-50nm scale, the aggressive scaling of MOSFETs is expected to culminate in dual-gate (DG) architectures on SOI substrates. DG MOSFETs are widely accepted to be the ultimate design that silicon can deliver in terms of on and off currents. So far, the design efforts on these novel structures have concentrated on ideal geometries and doping profiles. This paper describes the evolution of the SOI MOSFET from single-gate structures to multiple gate (double-gate, tri-gate, -gate, and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects are observed, which results in the need of developing quantum modeling tools for accurate prediction of the electrical characteristics of the devices. It also includes the effect of silicon thickness, when we are using multiple gates, the effects of different gate potentials on multiple gate MOSFETs, Doping concentration of Source/Drain/Channel region, thickness of SiO2 layer, and more.

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Journal: TechConnect Briefs
Volume: 1, Nanotechnology 2008: Materials, Fabrication, Particles, and Characterization – Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 1
Published: June 1, 2008
Pages: 284 - 287
Industry sector: Advanced Materials & Manufacturing
Topics: Composite Materials
ISBN: 978-1-4200-8503-7