Szermer M., Kotynia L., Pietrzak P., Janicki M., Napieralski A.
Technical University of Lodz, PL
Keywords: ASIC, many-core architecture, thermal coupling
The main goal of the paper is to present the design of an ASIC dedicated to thermal analysis of many-core architectures. Due to the fact that the process of designing real multi-core microprocessors is expensive and time consuming, the authors decided to design a special test ASIC which will be used (together with a dedicated simulator) to estimate thermal dependencies between cores in many-core processors. The presented ASIC consists of 384 heat cells which represent the power dissipation sources in real many-core microprocessors. These heat cells create a 10×24 array. The presented ASIC is a part of a project aimed at defining the thermal coupling coefficients between cores in many-core architectures using a dedicated thermal-logic simulator. The proposed ASIC will be used for empirical verification of this method. The full paper will present in detail the architecture and the simulation results of this ASIC.
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Published: June 18, 2012
Pages: 562 - 565
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Informatics, Modeling & Simulation
ISBN: 978-1-4665-6275-2