Finite Element Modeling and Simulation of Piezoelectric Energy Harvesters Fabricated in CMOS Technology


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Here we present a micron scale piezoelectric energy harvester fabricated in a commercial Complementary Metal Oxide Semiconductor (CMOS) technology. It is a trilayer cantilever model clamped on one end. The dimensions of this cantilever are 175 µm x 324 µm x 9 µm. The bottom layer is a Si substrate and the top layer is a ZnO thin film layer; sandwiched between them are Al interdigitated transducers (IDTs) on top of the dielectric SiO2. Finite element modeling and simulations are performed and results are compared with an equivalent circuit model and with the theory in the literature. Simulations of the energy harvester include detailed modal and harmonic analyses. Displacement and voltage distribution are studied at the first resonant frequency. The results demonstrate that commercial FEM software can be used to accurately design parameters such as material thickness, proof mass, IDT dimensions, etc. for novel piezoelectric energy harvester devices pre-fabrication.

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Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Published: June 18, 2012
Pages: 558 - 561
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Informatics, Modeling & Simulation
ISBN: 978-1-4665-6275-2