Castellated-Gate MOSFETs as Power Transistors for Nanometer CMOS and Post-CMOS Integrated Nanosystems

Seliskar J.J.
HiperSem Inc., US

Keywords: analog, CMOS, I/O, Interconnect, Mixed-Signal, nanosystem, PHY Layer

Analysis of the constant-voltage scaling characteristics of Fully-Depleted Castellated Gate (FDCG) MOSFETs reveals near term opportunities for these devices as the replacement for the “thick oxide” I/O device in CMOS System-On-A-Chip (SoC) technologies (e.g. the power transistor). Looking forward to the era of post-CMOS Integrated Nanosystems, FDCG MOSFETs utilized as PHY layer devices may provide the essential interoperable infrastructure for existing and yet-to-be-defined nanoscale devices.

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Journal: TechConnect Briefs
Volume: 1, Nanotechnology 2009: Fabrication, Particles, Characterization, MEMS, Electronics and Photonics
Published: May 3, 2009
Pages: 582 - 585
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Nanoelectronics, Photonic Materials & Devices
ISBN: 978-1-4398-1782-7