Carrier Transit Time Optimization of a High Speed Bipolar Transistor Using Numerical Device Simulation

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The optimization of bipolar transistors for high speed applications requires knowing the trade-off between several competing factors, including emitter-base junction charging time, base transit time, base-collector capacitance, high injection degradation, and collector debiasing [1]. Numerical device simulation (TCAD) is an effective tool in assisting this optimization because the relative merits of different structures and doping profiles can be assessed virtually without the need for physical prototypes, and because the device simulator allows direct access to fundamental physical quantities that cannot be easily measured. This paper demonstrates the application of a commercially available numerical device simulator [2] to optimizing the carrier transit time of a silicon NPN bipolar junction transistor (BJT). The device simulator was first calibrated to an existing BJT technology by suitably altering minority carrier lifetimes, surface recombination velocities, and mobilities in order to ensure a good match to DC and AC measurements. Structure and doping optimization of BJTs is not new [3], but the approach of analyzing transient charge storage using numerical device simulation is not widely practiced [4]. In particular, the engineering of the collector profile and its impact on high injection degradation and collector debiasing is considered here. Figure 1 shows the schematic cross-section of the device structure. The doping profile was first optimized in the intrinsic device. A transistor with a nonoptimized collector is presented here to better illustrate how device simulation can be used to identify causes of performance degradation. The modulation of the hole concentration from equilibrium (Fig. 2) shows two effects impacting the switching speed of the transistor: the charging of the emitter-base junction and the base push-out (Kirk effect) under high injection. The base push-out, in particular, is sensitive to the collector doping level and demonstrates the need for a higher doping concentration. The charge storage time tS, which is defined as the incremental change in electron concentration divided by the incremental change in electron current density, is a measure of the contribution of a region to the total carrier transit time tT of the device (Fig. 3). The integral of tS with respect to distance (Fig. 4) gives the total transit time, which is proportional to the reciprocal of the cutoff frequency f_. These figures show that the onset of base push-out corresponds to an increase in tS in the collector region and, consequently, tT. The debiasing of the collector, which is another consequence of its low doping concentration, is demonstrated by its Ohmic potential drop (Fig. 5) and resistance RC (Fig. 6). The need for increasing the collector doping is manifest, and a methodology for assessing alternate profiles is thus established. 2D studies of a device with an improved collector design were performed, and a comparison of simulated DC and AC electrical characteristics with measurements is available, and will be shown at the conference. Additional uses of TCAD for accelerating technology optimization and circuit performance assessment will be described at the conference.

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Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 52 - 55
Industry sector: Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 0-9728422-1-7