This study presents a nanometer-scale Integrate and Fire Spike (IFS) neuron cell using vertically-grown, undoped silicon nano-wire transistors. The design cycle starts with determining individual metal gate work functions for each NMOS and PMOS transistor to produce a 300mV threshold voltage. Wire radius and effective channel length are varied to find a common body geometry that yields smaller than 1pA OFF current and produces maximum ON currents for both transistors. Once the optimal device dimensions are defined, a spike neuron cell is built; its transient performance, power dissipation and layout area are measured. Post-layout simulation results indicate that worst-case power dissipation of the neuron is 1.44µW if a single synapse is connected at its output and increases by 18nW per synapse at 500MHz. The neuron circuit occupies approximately 0.116µm2.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 1
Published: May 20, 2007
Pages: 173 - 176
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topicss: Nanoelectronics, Photonic Materials & Devices