model reduction – TechConnect Briefs

Vector Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance

Pacelli A., SUNY-Stony Brook, US

We present a compact topology for inductive parasitics, using the vector potential as a state variable. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range [...]

Vector Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance

Pacelli A., SUNY-Stony Brook, US

We present a compact topology for inductive parasitics, using the vector potential as a state variable. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range [...]

Reduced Electro-Thermal Models for Integrated Circuits

Furmanczyk M., Napieralski A., Szaniawski K., Tylman W., Lara A., Technical University of Lodz, PL

Power dissipation density in today's integrated circuits makes thermal problems very important. Unfortunately, the electro-thennal co-simulations, which are often indispensable in solving thennal issues, are constrained by the lack of the IC's electro-thermal models. This [...]

CMOS MEMS and their Simulation

Korvink J.G., Emmenegger M., Taschini S., Baltes H., ETH Zürich, CH

The most appropriate tools for the modelling and simulation of MEMS are strongly related to the technology used to fabricate them. CMOS MEMS are naturally combined with circuitry, and in a packaged form they are [...]