logic – TechConnect Briefs

Hybrid Semiconductor/Nanoelectronic Circuit Architectures

Likharev K.K., Stony Brook University, US

I suggest to present a review of the recent work on hybrid semiconductor/nanodevice integrated circuits. Such a circuit combines a CMOS subsystem, fabricated with the usual lithographic patterning, and a nanowire crossbar with simple bistable [...]

Single-Crystal Nanowire Transistor for Logic and Memory Applications

Yu B., Ye L., Meyyappan M., NASA Ames Research Center, US

In this paper we report chemical synthesis, device fabrication, and device physics investigation of 1-D single-crystalline nanowire field-effect transistor (SNW-FET) for logic and memory applications. Wafer-scale transistor arrays were fabricated with semiconducting nanowires serve as [...]

Three-Dimensional Logic Architecture by Four-terminal Electrical Switches (FES) beyond Two-dimensional CMOS Architecture

Fujita S., Abe K., Lee T.H., Stanford University, US

The technology expected after the lithography limit to keep increasing the number of transistors is thought to be either use of new transistors such as CNT by bottom-up process or three-dimensional (3D) architecture. We have [...]