Hybrid Semiconductor/Nanoelectronic Circuit Architectures

,
,

Keywords: , , ,

I suggest to present a review of the recent work on hybrid semiconductor/nanodevice integrated circuits. Such a circuit combines a CMOS subsystem, fabricated with the usual lithographic patterning, and a nanowire crossbar with simple bistable two-terminal devices formed at each crosspoint, fabricated by advanced (e.g., nanoimprint) patterning. The CMOS and nano subsystems are connected with an area-distributed “CMOL” interface which allows the CMOS subsystem to address every nanodevice, even without nanoscale alignment of the two subsystems. Detailed simulations have shown that the hybrid circuits may serve as the basis for: (i) terabit-scale memories with access time below 100 ns and defect tolerance up to 10%, (ii) FPGA-like reconfigurable logic circuits with density about two orders of magnitude higher than that of CMOS FPGAs (fabricated with similar design rules), and (iii) mixed-signal neuromorphic networks (“CrossNets”) which may become the first hardware basis for challenging the human cerebral cortex in both areal density and speed. Recently the work on the hybrid CMOS/nano circuits received a strong boost from the experimental demonstration of highly reproducible metal-oxide devices with the necessary functionality and nanowire crossbars with sub-30-nm half-pitch. The work is supported in part by AFOSR, MARCO via FENA Center, and NSF.

PDF of paper:


Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 1
Published: May 20, 2007
Pages: 552 - 555
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Nanoelectronics
ISBN: 1-4200-6182-8