IIP3 – TechConnect Briefs

Linearity evaluation of Silicon Nanowire Surrounding Gate MOSFET for high performance ULSI applications

Aggarwal N., Sikka K., Gupta I., Chaujar R., Delhi Technological University, IN

The inspiration of this work is that the search for high performance ICs has led to scaling of MOSFETs down to sub-50nm regime and thus Silicon Nanowire (SNW) MOSFETs offer a promising solution for realizing [...]

Compact Modeling of Nonlinearities in Submicron MOSFETs

da Silva P.D., de Sousa F.R., Schneider M.C., Montoro C.G., Schneider M.C., Federal University of Santa Catarina, BR

Low power operation in RF CMOS circuits requiring low-distortion levels is often difficult to achieve due to the exponential relationship between drain current (IDS) and gate-to-source voltage (VGS) in subthreshold region. Our contribution in this work [...]