field plate – Page 2 – TechConnect Briefs

Simulation of Removal of Surface-State-Related Lag and Current Slump in GaAs FETs

Hafiz H., Kumeno M., Horio K., Shibaura Institute of Technology, JP

Two-dimensional transient analysis of field-plate GaAs MESFETs is performed in which surface states are considered. Quasi-pulsed current-voltage curves are derived from the transient characteristics. It is shown that drain lag and current slump due to [...]

Simulation of Decrease in Lag phenomena and Current Slump of Field-Plate GaAs FETs

Itagaki K., Ueda H., Terao Y., Horio K., Shibaura Institute of Technology, JP

Two-dimensional transient analysis of field-plate GaAs MESFETs is performed in which a deep donor “EL2” and a shallow acceptor are considered in a semi-insulating substrate, and the results are compared between the two cases with [...]

Simulation of Field-Plate Effects on Lag and Current Collapse in GaN-based FETs

Itagaki K., Nakajima A., Horio K., Shibaura Institute of Technology, JP

Two-dimensional transient analyses of field-plate GaN MESFETs and AlGaN/GaN HEMTs with a semi-insulating buffer layer have been performed in which a deep donor and a deep acceptor are considered in the buffer layer. Quasi-pulsed I-V [...]

Using ‘Adaptive Resurf’ Technique and Field Plate Working to Improve the Safe Operating Area of n-type Drain Extended MOS Transistors

Bakeroot B., Moens P., Vermandel M., Doutreloigne J., University of Gent, BE

Using TCAD, an n-type DEMOS (Drain Extended MOS) has been developed in a standard 0:35 mCMOS technology. The devices are optimised towards a Safe Operating Area (SOA) of 60 - 65 V using an n-type [...]