Sim S-P. – TechConnect Briefs

Unified RLC Model for On-Chip Interconnects

Sim S-P., Yang C., Santa Clara University, US

We present a unified RLC model for deep sub-micron on-chip interconnects. The model consists of two components, a quasi-3D capacitance extraction based on a novel concept of "effective width" and a effective loop inductance model. [...]

Investigation of the Mechanism of Floating Node Assisted CMOS Latch-Up

Sim S-P., Guo P., Kordesch A., Chen W.F., Liu C-M., Yang C.Y., Lee K., Santa Clara University, US

A new phenomenon of floating node assisted CMOS latch-up is experimentally observed and investigated using TCAD simulation. Using test structures having parasitic bipolar transistors and an electrically floating N+ diffusion node located at various distances [...]