Kumar M.J. – TechConnect Briefs

A Novel Dual Gate Strained-Silicon Channel Trench Power MOSFET For Improved Performance

Saxena R.S., Kumar M.J., Indian Institute of Technology, New Delhi, IN

We propose a new dual gate trench power MOSFET with strained Si channel that not only provides lower on resistance than the conventional trench MOSFET but also enables the in-circuit configurability of its characteristics for [...]

Tunnel Field Effect Transistor (TFET) with Strained Silicon Thinfilm Body for Enhanced Drain Current and Pragmatic Threshold Voltage

Kumar M.J., Saurabh S., Indian Institute of Technology, IN

Quantum tunneling devices are very promising as they have very low leakage current and show good scalability. However, the most serious drawback for tunneling devices hampering their wide-scale CMOS application is their low on-current and [...]

Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs

Nawal S., Venkataraman V., Kumar M.J., Indian Institute of Technology, IN

A simplae compact model for the threshold voltage of Strained Si/SiGe MOSFET is reported for the first time. This model accurately predicts the effects of Ge content and other device parameters on threshold voltage. The [...]

A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects

Kumar M.J., Venkataraman V., Gupta S.K., Indian Institute of Technology, IN

In this paper, we propose a novel device structure, known as the Grounded Laminated Gate (GLG) SOI MOSFET to eliminate the gate fringe field effects on the threshold voltage of short channel SOI MOSFETs. Our [...]

A New Lateral Trench Sidewall Schottky (LTSS) Rectifier on SOI

Singh Y., Kumar M.J., Indian Institute of Technology, IN

In this paper, a new Schottky rectifier structure, called Lateral Trench Sidewall Schottky (LTSS) rectifier on SOI is presented. Based on two-dimensional simulations, we demonstrate that the proposed device is superior in performance as compared [...]