A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects

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In this paper, we propose a novel device structure, known as the Grounded Laminated Gate (GLG) SOI MOSFET to eliminate the gate fringe field effects on the threshold voltage of short channel SOI MOSFETs. Our simulaton results demonstrate that the threshold voltage roll-off with increasing dielectric constant is effectively elminated in the proposed structure.

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Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 1
Published: May 7, 2006
Pages: 709 - 712
Industry sector: Advanced Materials & Manufacturing
Topics: Informatics, Modeling & Simulation
ISBN: 0-9767985-6-5