Jain F.C. – TechConnect Briefs

3-state Quantum Dot Gate FETs in Designing High Sampling Rate ADCs

Karmakar S., Chandy J.A., Jain F.C., University of Connecticut, US

In this work we present Cadence simulation of 3-bit Analog-to-Digital Converters (ADCs) based on compact 3-QDFET comparators, using 32nm design rules with BSIM 3.2.0 and BSIM 3.2.4 models [3]. In addition, we present the precise [...]

A Novel Nonvolatile Memory Using SiOx-Cladded Si Quantum Dots

Velampati R.S., Jain F.C., University of Connecticut, US

This paper presents characteristics of a novel quantum dot gate nonvolatile memory (QDNVM) whose threshold shift can be varied by adjusting the duration and magnitude of the Programming Voltage pulse applied at the drain end. [...]