3-state Quantum Dot Gate FETs in Designing High Sampling Rate ADCs

, ,

Keywords: , , , ,

In this work we present Cadence simulation of 3-bit Analog-to-Digital Converters (ADCs) based on compact 3-QDFET comparators, using 32nm design rules with BSIM 3.2.0 and BSIM 3.2.4 models [3]. In addition, we present the precise control of the threshold voltage of variable threshold voltage transistor which will remove R-2R ladder problem in conventional analog-to-digital converters(ADCs).

PDF of paper:

Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 21, 2010
Pages: 17 - 20
Industry sector: Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 978-1-4398-3402-2