Dutton R. – TechConnect Briefs

Modeling of FET Flicker Noise and Impact of Technology Scaling

Chen C-Y, Liu Y., Cao S., Dutton R., Sato-Iwanaga J., Inoue A., Sorada H., Stanford University, US

Ongoing scaling of device dimensions, including the introduction of new channel materials and device structures, as well as the incorporation of novel gate-stack materials, has major implications on noise performance metrics. In particular, flicker noise [...]

Changing the Paradigm for Compact Model Integration in Circuit Simulators Using Verilog-A

Mierzwinsk M., Halloran P.O., Troyanovsky B., Dutton R., Tiburon Design Automation, Inc., US

Verilog-A has been demonstrated to be a suitable language to describe analog models. However, effective adoption by both the Electronic Design Automation (EDA) industry and end users requires that the language implementation provide all of [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]