National Chiao Tung University – Page 5

Impacts of High-k Offset Spacer on 65-nm Node SOI Devices

Ma M-W, Chao T-S., Kao K-S, Huang J-S, Lei T-F, National Chiao Tung University, TW

In this paper, the 65-nm node SOI devices with high-k offset spacer was investigated. Calculated results show that the high-k offset spacer can effectively increase Ion and reduce Ioff due to the high vertical fringing [...]

Opitimal Developing Policies of Nanotechnology in Taiwan

Hung C-Y, Yang J-R, Kao L-H, Chiou H-K, National Chiao Tung University, TW

This research tends to propose an optimal executing order of developing policies in nanotechnology domain. By using the multi-objective compromise optimization method which integrating AHP with TOPSIS, we can conduct a priority of government policies [...]

A Parallel Intelligent OPC Technique for Design and Fabrication of VLSI Circuit

Yu S-M., Li Y., National Chiao Tung University, TW

Optical lithography is the key technology used in very large scale integrated (VLSI) circuit and systemon- a-chip (SoC) fabrication [1-3]. The exposure on wafer has distortions due to the proximity effects. Hence, a correction of [...]

A Two-Dimensional Numerical Simulation of Organic Light-Emitting Devices

Li Y., Lee B-S, Lee J.W., Chen P., Chen W-H, Lee B-S, Lee J.W., Lu C-S, Chen P., Chen W-H, National Chiao Tung University, TW

Organic light-emitting devices (OLEDs) add a completely new dimension to current display technology [1-3]. OLED displays are thinner, lighter, brighter, and cheaper to manufacture; which also consume less power than the current thin displays do. [...]

A Novel SPICE Compatible Current Model for OLED Circuit Simulation

Li Y., Lee B-S, Lee J.W., Lee B-S, Lee J.W., Lu C-S, Chen W-H, National Chiao Tung University, TW

high quality, and low power consumption display [1-2]. It is known that the brightness of the OLED is controlled by the current density of the device; therefore, precisely controlling the current density of active matrix [...]

A Unified Compact Model for Electrostatic Discharge Protection Device Simulation

Chou H-M, Cho Y-Y, Chou H-M, Lee J.W., Li Y., National Chiao Tung University, TW

In modern microelectronics manufacturing, whole chip electrostatic discharge (ESD) protection circuit design is necessary for obtaining robust electrical performance [1-5]. In designing the whole chip ESD protection circuit, owing to its high circuit complexity, an [...]

Spin Dependent Boundary Conditions and Spin Splitting in Cylindrical Quantum Dots

Li Y., Liu J-L., Voskoboynikov O., Liu J-L., Lee C.P., Sze S.M., National Chiao Tung University, TW

To study a spin dependence of the electron energy states in tree dimensional cylindrical semiconductor dots we consider theoretically the spin-orbit interaction impact on the electron quantum con...nement in the dots. We solve the problem [...]

Parallel Dynamic Load Balancing for Semiconductor Device Simulations on a Linux Cluster

Li Y., Lin S-S., Liu J-L., Lin S-S., Yu S-M., Liu J-L., Chao T-S., Sze S.M., National Chiao Tung University, TW

A parallel dynamic load balancing for 2-D and 3-D semiconductor device simulations is proposed. The hydrodynamic and drift diffusion models are discretized and solved with finite volume (box) and monotone iterative methods. Dynamic load balancing [...]