Dutton R.W., Choi C-H
Stanford, US
Keywords: capacitance, ESD, STI, strained Si, stress
Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the active region is scaled from Lactive=0.4 µm to 0.1 µm. Mobility can be lower by 50 % for narrow active widths resulting from the strain relaxation. The strain relaxation may restrict the use of strained-Si MOSFETs for technology nodes beyond 25 nm. Electrical and thermal characteristics of strained-Si devices are investigated and a compact junction capacitance model for strained-Si MOSFET suitable for circuit simulation is proposed.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2005 Workshop on Compact Modeling
Published: May 8, 2005
Pages: 215 - 218
Industry sector: Sensors, MEMS, Electronics
Topic: WCM - Compact Modeling
ISBN: 0-9767985-3-0