This paper describes using wide energy gap lattice-matched II-VI layers, such as ZnSeTe- ZnMgSeTe, serving as a high-k gate dielectric for n-channel enhancement mode InGaAs field effect transistors (FETs). The thrust is to reduce interface states at the channel-gate insulator boundary while providing sufficient barrier height to confine the carriers in the channel created by inversion. In addition, this paper describes the role of various types of cladded quantum dots incorporated in the gate region to achieve either 3-state FET operation or nonvolatile memories. The fabrication methodology involves the growth of II-VI insulators using metalorganic chemical vapor deposition (MOCVD) and site-specific self assembly of GeOx-Ge and SiOx-Si cladded quantum dot forming the gate region.
Journal: TechConnect Briefs
Volume: 1, Nanotechnology 2009: Fabrication, Particles, Characterization, MEMS, Electronics and Photonics
Published: May 3, 2009
Pages: 598 - 601
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topicss: Nanoelectronics, Photonic Materials & Devices