Modeling Strategies for Flash Memory Devices

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Flash memories are one of the most pervasive components of today electronic systems. The continuous scaling of the memory device opened new issues with regards to sensitivity of the cell threshold voltage to degradation mechanisms or to capacitive coupling between FGs of adjacent cells in NAND architectures. In this scenario, accurate Spice-like models are strongly needed to enable the designers to effectively explore optimized algorithms and ancillary circuit solutions for read and program/erase (P/E) operations, especially when considering multi-level applications. In this paper, we will review the compact modeling strategies for standard and advanced Flash memory devices. We will illustrate the methods used to calculate the FG potential in steady-state conditions and to include tunneling currents across the tunnel oxide for transient simulations of program/erase operations and reliability effects related to the degradation mechanisms of the tunnel dielectric. The model will be used for the circuit simulation of NAND strings, being able to correctly take into account the capacitive coupling between adjacent cells. Finally, we will show how the same model framework can be used for the simulation of advanced charge-trapping devices.

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Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 13, 2011
Pages: 762 - 767
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 978-1-4398-7139-3