Kwon O., Yoon S., Ban Y., Won T.
Inha University, KR
Keywords: deposition, DRAM, etching., modeling, parallel computation, process integration, process simulation, topography
In this paper, we present a 3D topography simulator, so-called 3D-SURFILER(SURface proFILER), to model a complicated 3D structure on the substrate for gigabit DRAMs. The 3D-SURFILER comprises a deposition and etching simulator employing a cell advancing scheme and a parallel computational numerical engine. An MIM (Metal-Insulator-Metal) stacked capacitor [1] has been chosen to verify the validity of the simulator.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
Published: March 27, 2000
Pages: 688 - 691
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems
ISBN: 0-9666135-7-0