Modeling of breakdown phenomena is becoming central problem in today’s design of high-speed bipolar circuits. It is especially important for the output stages that should simultaneously provide speed and output signal power. To this end, an accurate modeling is essential to fully exploit the potential of the advanced Si and SiGe bipolar technologies, and to allow safe circuit design with bipolar transistors operating above the breakdown voltage. Carrier impact ionization could change the direction and significantly increase the intensity of a transistor base current leading also to instabilities in the device behavior. One way to address multidimensional avalanche effects in circuit design is to employ sectionized bipolar transistor models. The network of intrinsic transistor is capable of capturing the distributed character of the main transistor current, but its main drawback is the complexity. A novel technique to significantly reduce the computational cost of sectionalized transistor models is proposed in this paper. A proposed method employs only two one-dimensional chains of transistor sections along the symmetry lines of the emitter contact plus one transistor in the corner using bilinear interpolation to get the effect of full transistor matrix. The original and reduced segmentated models have been practically implemented and compared.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 20, 2007
Pages: 658 - 661
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling