A Gate Layout Technique for Area Reduction in Nano-Wire Circuit Design


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An strategy for developing integrated circuits with many individual nanodevices has yet to be formulated. This paper presents an homogeneous (array-based) approach for designing and manufacturing digital circuits using nanotubes or nanowires. By targeting contacts which occupy large area, and using a novel high level combinatorial formulation for area, substantial savings is obtained in physical mask layouts. The ultimate objective is to provide a further insight on the applicability of Moore’s law to nanotechnology by evaluating the effects of area in logic circuit design.

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Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 2
Published: May 8, 2005
Pages: 471 - 474
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: MEMS & NEMS Devices, Modeling & Applications
ISBN: 0-9767985-1-4