ultra-low-power – TechConnect Briefs

Static Analog Design Methodology

Guigues F., Rudolff F., Kussener E., L2MP UMR 6137 CNRS - ISEN-Toulon, FR

When strong constraints of supply voltage (< 1V ) and bias current (< 100nA) are required, the only way to meet design’sspecifications without using huge silicon area consists on decreasing transistor’s inversion level and therefore [...]

Automatic Device Design Optimization with TCAD Frameworks

Stockinger M., Selberherr S., Technical University of Vienna, AT

A design optimization method is presented which utilizes automatic optimization capabilities within TCAD frameworks. This method is applied to doping profile optimizations of ultra-low-power CMOS transistors with 0.25 and 0.1 um gate lengths. Two different [...]