silicon nanowire (SiNW) – TechConnect Briefs

Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs

Zhou X., Nanyang Technological University, SG

This paper presents a unified compact model (Xsim) for bulk/SOI MOSFETs, double-gate (DG) FinFETs, and gate-all-around (GAA) silicon-nanowires (SiNWs) that has been under development over the past 13 years. One key feature of the model [...]

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Zhou X., Zhu G.J., Srikanth M.K., Lin S-H, Chen Z.H., Zhang J.B., Wei C.Q., Yan Y.F., Selvakumar R., Nanyang Technological University, SG

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The [...]

Synthesis and Characterization of Templated Si-based Nanowires for Electrical Transport

Lee J-H., Carpenter M., Eisenbraun E., Xue Y., Geer R., University at Albany - State University of New York, US

Self-assembled Si nanowires (SiNWs) have been synthesized and characterized as a template for surface metal silicide formation to investigate confinement of electron transport at the nanowire surface. Silicon nanowires with diameters ranging from 5 to [...]