JFET – TechConnect Briefs

Bonding Pad with Reduced Capacity

Mats I., Tarcenco V., Select Techno-Fix Ltd, CA

The technical solutions for the Integrated Circuits (ICs) packaging remains enough conservative during microelectronics development. The ICs with active components having size of micrometers or even nanometers continue to have bonding pads area within hundreds [...]

R3, an Accurate JFET and 3-Terminal Diffused Resistor Model

McAndrew C., Motorola, US

This paper presents an improved compact model for diffused resistors and JFETs, valid over geometry, bias, and temperature. The model includes a physically based junction depletion model, a new and accurate velocity saturation model derived [...]

R3, an Accurate JFET and 3-Terminal Diffused Resistor Model

McAndrew C., Motorola, US

This paper presents an improved compact model for diffused resistors and JFETs, valid over geometry, bias, and temperature. The model includes a physically based junction depletion model, a new and accurate velocity saturation model derived [...]

Self Aligned Gate JFETs for Smart MEMS

Amon S., Vrtacnik D., Resnik D., Krizaj D., Aljancic U., Levstek A., University of Ljubljana, SI

Self Aligned Gate JFET (SJFET) devices and circuits are reported. The problem of electrical isolation between devices on the same chip is realized through Self Aligned Gate approach, enabling the application of standard bipolar discrete [...]