CV – TechConnect Briefs

Fabrication of Electroless Plated Nano Porous Gold Film for Trace Heavy Metal Ion Detection In Sensor Applications

Bhagavathula S., Ramanan S.R., Kim S.K., Krishnan J.N., BITS Pilani, K. K. Birla Goa Campus, IN

Nano porous gold film was fabricated by electroless plating with Potassium Gold Cyanide as plating solution. E-beam deposited Cu substrates were chosen for plating. The electroless plated gold was investigated through XRD and SEM. SEM [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R.W., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]

Simple Method of Characterizing CMOS Channel Dopant Profiles Using CV Technique

Kapila D., Kulkarni M., Fernando C., Davis J., Vasanth K., Pollack G., Texas Instruments, Inc., US

In CMOS process and device simulations, characterization of complete dopant profiles in the channel region is essential for accurate simulations. We have developed a simple, fast and inexpensive methodology for characterizing CMOS channel dopant profiles [...]