O’uchi S. – TechConnect Briefs

Source/Drain Edge Modeling for DG MOSFET Compact Model

Nakagawa T., O’uchi S., Sekigawa T., Tsutsumi T., Hioki M., Koike H., AIST (National Institute of Advanced Industrial Science and Technology), JP

A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]

Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices

Nakagawa T., Sekigawa T., Tsutsumi T., Liu Y., Hioki M., O’uchi S., Koike H., Electroinformatics Group, JP

We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two [...]

Transition Point Consideration for Velocity Saturating Four-terminal DG MOSFET Compact Model

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., O’uchi S., Koike H., AIST, JP

We have proposed a compact model for four-terminal DG MOSFETs based on double charge-sheet model, with the velocity saturation effect as a function of carrier density profile inside the channel, with explicit handling of drain [...]

Capacitance Model for Four-Terminal DG MOSFETs

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., O’uchi S., Koike H., National Institute of Advanced Industrial Science and Technology, JP

We present an intrinsic-capacitance model for undoped-channel full-deplete DG MOSFETs with two independent gates of different gate-oxide thickness. It includes carrier-velocity saturation, and mobility change by the surface electric-field. We considered five intrinsic capacitances Cg1s, [...]