Gupta R.S. – Page 2 – TechConnect Briefs

Pre-Distortion Assessment of Workfunction Engineered Multilayer Dielectric Design of DMG ISE SON MOSFET

Kaur R., Chaujar R., Saxena M., Gupta R.S., Semiconductor Devices Research Laboratory, IN

To overcome miniaturization roadblock, innovative architectural enhancements involving the use of an improved SOI like architecture called Silicon On Nothing (SON) capable of SCE and DIBL suppression onto the existing ISE devices [2], has been [...]

Assessment of L-DUMGAC MOSFET for High Performance RF Applications with Intrinsic Delay and Stability as Design Tools

Chaujar R., Kaur R., Saxena M., Gupta M., Gupta R.S., Gupta M., Gupta R.S., Semiconductor Devices Research Laboratory, IN

The paper assesses RF performance of L-DUMGAC MOSFET using ATLAS device simulator by performing AC simulations at very high frequencies, hence, proving its efficacy for high performance RF applications. Higher Gma & K; and lower [...]

Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability

Goel K., Saxena M., Gupta M., Gupta R.S., Gupta M., Gupta R.S., Professor, IN

We have modeled a new structure TRIMGAS which has 3 gate materials in the gate and an oxide stack. we have compared various parameters to see whether this strucure is superior to any of our [...]