Fujioka H. – TechConnect Briefs

Fail Pattern Classification and Analysis System of Memory Fail Bit Maps

Nakamae K., Itoh A., Fujioka H., Osaka University, JP

In order to determine problematic wafer processing steps rapidly during memory production, the system that classifies failure patterns from memory fail bit maps (FBMs) and estimates the cause of failure is proposed. The system mainly [...]

Wafer Fabrication Process Simulation Including Cost: Which Should be Used in an In-Line Wafer Inspection Strategy, High Sensitivity and High Cost Inspection Machine or Low Sensitivity and Low Cost Inspection Machine?

Nakamae K., Yamaji S., Fujioka H., Osaka University, JP

By combing an event-driven simulation method including costs and a simple VLSI particle-induced yield predictor, we discuss that which should be used in an in-line wafer inspection strategy, a high sensitivity & high cost inspection [...]

A Simple VLSI Spherical Particle-Induced Yield Predictor

Nakamae K., Ohmori H., Fujioka H., Osaka University, JP

A simple VLSI particle-induced yield predictor has been developed that allows us to predict the entire yield of VLSI and also to analyze the bottleneck processing steps and faults. Particles with spherical shape are generated [...]