By combing an event-driven simulation method including costs and a simple VLSI particle-induced yield predictor, we discuss that which should be used in an in-line wafer inspection strategy, a high sensitivity & high cost inspection machine or a low sensitivity & low cost inspection machine. Two segments of a DRAM fab line including the inspection and the defect sourcing stages are modeled. Simulated results show that setting an adequate wafer rejection condition and selecting a proper sampling plan obtain the minimum cost per chip regardless of the kind of inspection machine.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
Published: March 27, 2000
Pages: 700 - 703
Industry sector: Sensors, MEMS, Electronics
Topics: Modeling & Simulation of Microsystems