Cadence Design Systems – TechConnect Briefs

Modeling and Characterization of Wire Inductance for High Speed VLSI Design

Arora N.D., Song L., Cadence Design Systems, US

Ever increasing circuit density, operating speed, faster on-chip rise times, use of low resistance Copper (Cu) interconnects, and longer wire lengths due to high level of integration in VLSI chip designs, have necessitated the need [...]

Modeling and Characterization of High Frequency Effects in ULSI Interconnects

Arora N.D., Song L., Cadence Design Systems, US

This paper discusses the accurate modeling of resistance R, inductance L and capacitance C in sub-100nm process node and their impacts on high frequency effects such as delay, crosstalk, and power/ground bounce. Models of interconnect [...]

Modeling and Characterization of Wire Inductance for High Speed VLSI Design

Arora N.D., Song L., Cadence Design Systems, US

Ever increasing circuit density, operating speed, faster on-chip rise times, use of low resistance Copper (Cu) interconnects, and longer wire lengths due to high level of integration in VLSI chip designs, have necessitated the need [...]