Integrating molecular memory devices into large scale arrays is a key requirement for translating the miniature size of molecular devices into ultradense memory systems. This in turn imposes constraints on the individual molecular memory devices. A circuit theory approach is used to derive a general parameterized memory circuit model, from which quantitative relationships between the device on:off ratio, noise margin and memory size are studied. Assuming a small interconnect impedance and a reasonable noise margin, a 7:1 on:off ratio would be sufficient for a 4kbit memory, while a 16kbit memory would require a 13:1 ratio. Parasitic impedances become significant in architectures employing molecular interconnect, and full-scale memory circuit simulations are presented as a case study. This way, trends for the impact of all system parameters on system scalability are examined.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: March 7, 2004
Pages: 61 - 64
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics