The geometry dependence of the leakage current by modeling the effect of source/drain extension asymmetry on the leakage current of CNTFETs with 20 nm wrap-around gates is investigated. The symmetric geometry has the highest leakage current. The asymmetric geometry with drain extension fixed to 4 nm results in the next highest leakage. The asymmetric geometry with source extension fixed to 4 nm results in the lowest leakage. This configuration blocks the inter-band tunneling at the high field region of the drain. The best device has a high ON/OFF current ratio (~1E6) and inverse subthreshold slope close to the ideal value (~63 mV/dec).
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 8, 2005
Pages: 136 - 139
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Carbon Nano Structures & Devices, Nanoelectronics