Horio K., Mitani Y., Wakabayashi A.
Shibaura Institute of Technology, JP
Keywords: buried gate, GaAs MESFET, gate lag, recessed gate, surface state
We have made two-dimensional simulation of turn-on characteristics of recessed-gate and buried-gate GaAs MESFETs, and studied how the gate-lag or the slow current transient (which may occur due to surface states) is affected by the recess-structural parameters and the off-state gate voltage VGoff . It is shown that when VGoff is around the threshold voltage (pinch-off voltage) Vth, the gate-lag could be greatly reduced by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when VGoff is much more negative than Vth.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems
Published: March 19, 2001
Pages: 510 - 513
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems
ISBN: 0-9708275-0-4