Tanaka T., Itagaki K., Nakajima A., Horio K.
Shibaura Institute of Technology, JP
Keywords: drain lag, GaAs FET, gate lag, power slump, surface state
In this study, we carry out two-dimensional transient analysis of field-plate GaAs MESFETs by taking surface states into account. Quasi-pulsed current-voltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and SiO2 passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and SiO2 layer thickness.
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 13, 2011
Pages: 595 - 598
Industry sector: Advanced Materials & Manufacturing
Topic: Informatics, Modeling & Simulation
ISBN: 978-1-4398-7139-3