Nanocomputer Systems Engineering

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Regardless of whichever precise nano-device technology ends up being most viable for general-purpose computing, the design of densely-packed computer systems comprised of nanometer-scale bit-devices offers a number of interesting new challenges for the field of computer systems engineering. The thorough optimization of overall cost-efficiency in ambitious, high-performance nanocomputing systems requires a unified consideration of concerns in many areas, including hardware cost, power delivery and heat removal, synchronization, error correction, communications, logic architectures, and HW/SW algorithms (including the possible impact of reversible & quantum algorithms). In this paper, we survey some of the key foundational principles and analytical tools that will be essential for carrying out this important future enterprise of nanocomputer systems engineering. We show that useful analytical results can already be obtained regarding the nature and scalability of the optimal computer architectures and algorithms, results that are qualitatively nearly independent of the particular choice of device technology. The overall cost-efficiency of a system design can then be expressed as a quantitative function of generic, abstract bit-device parameters, giving device physicists a valuable analytical tool that they can use to compare and optimize their low-level device mechanisms so as to obtain the best overall system-level cost-efficiency.

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Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 182 - 185
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems
ISBN: 0-9728422-1-7