Hall J., Luo Z., Xiao Y., Young A., Connerney D.
Fairchild Semiconductor, US
Keywords: analog, breakdown, CADENCE, EOS, high-voltage, integration, Interface, LDMOS, methodology, Mixed-Signal, MOSFET, Power, predictability, safe operating area, simulation, SOA, spectre
Circuit simulations involving power devices often require additional checks comparing with generic low power applications. The burden lies with the individual designers to ensure that the power transistors are operating well within the Safe Operating Area (SOA). However, it is not trivial to perform such checks due to the inherit limitations of industry standard MOS models: inadequate diode model for the junctions, non-existence of junction breakdowns, and alert when such breakdown voltages are reached. In this paper, we have created two subcircuits, with BSIM and HiSIM-LD based POWER MOSFET Models with a behavioral current source conforming to the SOA contour extracted from the pulse measurements. An additional warning system built-in to the Cadence Spectre Simulator, the designer will be able to catch both transient spikes and dynamic breakdowns (function of Vgs and Vds) outside of the SOA of the Power MOSFET; both by an output logfile of circuit nodes and the associated time intervals where they are outside of the SOA region, and visually where the breakdown anomalies are observable due to the behavioral current source within the subcircuit model. This methodology can be easily generalized to other devices for the circuits of interest.
Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2009: Biofuels, Renewable Energy, Coatings, Fluidics and Compact Modeling
Published: May 3, 2009
Pages: 651 - 654
Industry sector: Sensors, MEMS, Electronics
Topic: WCM - Compact Modeling
ISBN: 978-1-4398-1784-1