By the time CMOS reaches its physical scaling limits in the next several years, computing will have very likely evolved to meet the demands imposed with increases in application complexity and the processing of enormous amount of digital information. This evolution has been rapid and constant and can currently be seen in computing architectures in the form of multi-core processors, GPU based parallel computing, interconnected computing clusters, and hybrid architectures which utilize parallel and scalar processors to increase computing efficiencies. Many designs, which have been proposed to replace CMOS and continue the scaling of computing devices, have largely underappreciated the recent move to this type of computing. This work seeks to develop an architecture suited for the future of nano-scale computing by creating a new architecture capable of high speed, low power, molecularly scalable, fault-tolerant, reconfigurable, reversible, and parallel computing.
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 21, 2010
Pages: 79 - 82
Industry sector: Sensors, MEMS, Electronics