VHDL – TechConnect Briefs

VHDL Simulation considering Single Event Upsets (SEUs)

Grecki M., Technical University of Lodz, PL

The SEEs can be destructive for semiconductor devices, however non-destructive SEE called SEU ( Single Event Upsets) resulting of bit flips seems to be the main problem. Due to reduction of feature size the SEUs [...]

Hardware Realization of Biological Mechanisms Using VHDL and FPGAs

Botros N., Akaaboune M., Alghazo J., Alhreish M., Southern Illinois University, US

In this paper we present a hardware realization of a simplified blood-pressure regulation mechanism. The mechanism has been proposed and then modeled by using Hardware Description Language (VHDL). After verifying the simulation results, Computer Aided [...]

Simulation of Mixed-Signal Systems in Standard VHDL

Grätz H., Fischer W-J, Fraunhofer-Institute of Microelectronic Circuits and Systems, DE

Historically, the analogue and digital parts of a hardware design have been modelled and simulated in different environments and could not be combined in a single simulator. On the other hand, if a design contains [...]