feature-scale – TechConnect Briefs

Feature Length-Scale Modeling of LPCVD and PECVD MEMS Fabrication Processes

Musson L.C., Ho P., Plimpton S.J., Schmidt R.C., Sandia National Laboratories, US

The surface micromachining processes used to manufacture MEMS devices and integrated circuits transpire at such small length scales and are sufficiently complex that theoretical analysis of them is particularly inviting. Under development at Sandia National [...]

MEMS Fabrication Modeling with ChISELS: A Massively Parallel 3-D Level-Set Based Feature Scale Modeler

Musson L.C., Plimpton S.J., Schmidt R.C., Sandia National Laboratories, US

We are developing ChISELS (Chemically Induced Surface Evolution with Level-Sets), a parallel code to model 3-D material depositions and etches at feature scales on patterned wafers at low pressures. ChISELS is a platform on which [...]

Nanoworld Semiconductor Industry – State and Future Challenges of Technology Computer Aided Design

Puchner H., Cypress Semiconductor, US

Several application examples of nanoscale techniques used to influence or enhance the understanding of material properties as well as processing behavior are presented. We will also present a review of first principle density functional theory [...]

Nanoworld Semiconductor Industry – State and Future Challenges of Technology Computer Aided Design

Puchner H., Cypress Semiconductor, US

Several application examples of nanoscale techniques used to influence or enhance the understanding of material properties as well as processing behavior are presented. We will also present a review of first principle density functional theory [...]